1. Field of the Invention
The present invention relates to a method and apparatus for controlling a memory.
2. Description of the Related Art
With the progress in the miniaturization and the high-speed in the field of semiconductor technologies, smaller memory elements have been used in random access memories (RAMs) mounted on a processor, such as central processing units (CPUs). Such a smaller memory element, however, may cause a failure, such as bit inversion, in data stored in the RAM. As one of approaches to automatically take an action in response to such a failure, researchers have studied about a reliability, availability, and serviceability control (RAS control).
An error correction technique by using an error correcting code (ECC), for example, plays an important role in the RAS control. In a typical error correction technique, an error correcting circuit corrects an error in data, such as bit inversion, by using the ECC added to the data. Such error correction is performed on the assumption that the error correcting circuit is normal. Therefore, it is necessary to guarantee reliability of the error correcting circuit.
In an approach to verify whether the error correcting circuit is normal, data including an error is intentionally written to the RAM. If the error correcting circuit detects the error from the data, the error correcting circuit is determined to be normal. For example, in a conventional technology disclosed in Japanese Patent Application Laid-open No. H07-84889, the data is written to a first address of the RAM, and the error data is written to a second address that is obtained by inverting the first address. Whether the error correcting circuit is normal is determined by using the error data written to the second address.
In the conventional technology, however, the error data is generated intentionally only when the data is written to the RAM. Therefore, if the RAM is used as a cache memory in a CPU, the reliability of the error correcting circuit is not always guaranteed because, for example, the error data may be overwritten with new data without being read from the RAM. Specifically, to verify the validity of the error correcting circuit, an error is generated in the data to be written to the RAM, and then the error data is written to the RAM. When a read command is issued to read the error data, the error correction is performed on the error data, so that it is possible to determine whether the error is properly detected and corrected. However, if the error data is overwritten with new data without being read from the RAM, the new data is read from the RAM instead of the error data.
If there is a relatively long interval between when the error data is written to the cache memory and when the error data is read from the cache memory, checking of the error correcting circuit is not always conducted regularly. As a result, the reliability of the error correcting circuit is not always guaranteed.